Why are multiple levels of cache used (L1, L2, L3) in a memory subsystem?

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Multiple Choice

Why are multiple levels of cache used (L1, L2, L3) in a memory subsystem?

Multiple levels of cache exist to dramatically cut the time it takes to fetch data for the CPU by keeping the most useful data closer to the processor, taking advantage of locality at different distances from the core. The L1 cache is tiny but extremely fast, holding the most frequently used data and instructions. If the needed item isn’t in L1, the system checks the L2 cache, which is larger and a bit slower but still much faster than main memory. If it isn’t there, it goes to the L3 cache, which is even larger and may be shared among cores. Only after that does it fetch from main memory. This tiered approach lowers the average memory access time because most requests are satisfied by a nearby level, while the less frequent misses pay the higher latency only when necessary. Understanding locality helps: temporal locality means data recently used is likely to be used again soon, and spatial locality means nearby data is likely to be used soon. The cache hierarchy captures both kinds of locality efficiently across different sizes and latencies, balancing speed, size, and cost. The other options don’t fit because cache levels aren’t about disk transfer rates, redundancy, or replacing registers. They’re about hiding main memory latency by keeping progressively more data closer to the CPU.

Multiple levels of cache exist to dramatically cut the time it takes to fetch data for the CPU by keeping the most useful data closer to the processor, taking advantage of locality at different distances from the core. The L1 cache is tiny but extremely fast, holding the most frequently used data and instructions. If the needed item isn’t in L1, the system checks the L2 cache, which is larger and a bit slower but still much faster than main memory. If it isn’t there, it goes to the L3 cache, which is even larger and may be shared among cores. Only after that does it fetch from main memory. This tiered approach lowers the average memory access time because most requests are satisfied by a nearby level, while the less frequent misses pay the higher latency only when necessary.

Understanding locality helps: temporal locality means data recently used is likely to be used again soon, and spatial locality means nearby data is likely to be used soon. The cache hierarchy captures both kinds of locality efficiently across different sizes and latencies, balancing speed, size, and cost.

The other options don’t fit because cache levels aren’t about disk transfer rates, redundancy, or replacing registers. They’re about hiding main memory latency by keeping progressively more data closer to the CPU.

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